Nonvolatile memory devices having improved read reliability
US8743604B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 20, 2011 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Jan 7, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5646
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory systems include at least one nonvolatile memory array having a plurality of rows of nonvolatile multi-bit (e.g., N-bit, where N>2) memory cells therein. A control circuit is also provided, which is electrically coupled to the nonvolatile memory array. The control circuit is configured to program at least two pages of data into a first row of nonvolatile multi-bit memory cells in the nonvolatile memory array using a first sequence of read voltages to verify accuracy of the data stored within the first row. The control circuit is also configured to read the at least two pages of data from the first row using a second sequence of read voltages that is different from the first sequence of read voltages. Each of the read voltages in the first sequence of read voltages may be equivalent in magnitude to a corresponding read voltage in the second sequence of read voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.