Generic low power strobe based system and method for interfacing memory controller and source synchronous memory
US8743634B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2011 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Apr 3, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for interfacing a memory controller and a source synchronous memory utilizing a generic low power strobe. A set of double rate (2×) strobes can be generated by gating a continuous double rate clock in order to enable the set of double rate strobes only for duration of a data transfer from controller to the memory. The data and control from a SDR continuous single rate (1×) clock domain with respect to the memory controller can be moved to a set of double rate clock domain by sampling with the set of double rate strobes. The phase of the set of double rate strobes can be shifted in relation to the continuous single rate clock and a phase relationship of the generated synchronous signals to the memory can be dynamically switched by changing the phase of the set of double rate strobes. The set of double rate clock domain enables each bit-slice to be independently programmed to generate an output to the memory at each phase relative to the controller single rate clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.