Memory controller for strobe-based memory systems
US8743635B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2012 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Aug 2, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller for strobe-based memory systems is disclosed. The memory controller includes a circuit to generate a control signal having a predetermined timing relationship with respect to a first clock signal, a circuit to receive the control signal, and a receiver to sample the read data in response to the qualified read strobe signal. The receiving circuit includes an input to receive an external read strobe signal transmitted by a semiconductor memory device, circuitry to synchronize the control signal and the received read strobe signal to have a common timing relationship with respect to each other, and circuitry to gate the read strobe signal based on the synchronized control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.