Reducing dynamic power consumption of a memory circuit
US8743653B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2012 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Nov 17, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit can include address evaluation circuitry coupled to an address bus of a memory and configured to generate a first control signal responsive to determining that an address on the address bus has not changed for a current clock cycle from a previous clock cycle. The circuit can include write enable evaluation circuitry coupled to the memory and configured to generate a second control signal responsive to determining that a write enable signal of the memory is de-asserted for the current clock cycle and for the previous clock cycle. The circuit can include clock enable circuitry coupled to a clock enable port of the memory and configured to generate a clock enable signal to the clock enable port of the memory responsive to the first control signal and the second control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.