Pseudo-random bit sequence generator
US8745113B2 · kind B2 · utility
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14References
16Claims
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Key dates
| Filing date | Jul 1, 2009 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Aug 1, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/581
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a pseudo-random bit sequence (PRBS) generator which outputs the entire datapath, or entire pseudo-random bit sequence, over one single clock cycle. This is accomplished by removing redundancy, or any redundant exclusive-or gates from linear feedback shift registers; using logic to identify the critical path and optimal shift for the critical path; and dividing the datapath into several pipeline stages to increase the clock rate (i.e., transmission speed).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.