Altera Canada Co.
20Patents
20Active
20Granted
46Portfolio score
Filing activity: Nov 29, 2007 → Apr 2, 2014 · 7 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8359518B2 | 2D product code and method for detecting false decoding errors | Electricity | 5 | Active |
| US8254378B2 | Strict-sense minimal spanning switch non-blocking architecture | Electricity | 3 | Active |
| US8136020B2 | Forward error correction CODEC | Electricity | 3 | Active |
| US8705581B1 | Method of multiple lane distribution (MLD) deskew | Electricity | 3 | Active |
| US8199782B2 | Method of multiple lane distribution (MLD) deskew | Electricity | 2 | Active |
| US8498370B2 | Method and apparatus for deskewing data transmissions | Electricity | 1 | Active |
| US8363684B2 | Method of multiple lane distribution (MLD) deskew | Electricity | 1 | Active |
| US8385472B2 | Context-sensitive overhead processor | Electricity | 1 | Active |
| US8238349B2 | Method of accessing stored information in multi-framed data transmissions | Electricity | 1 | Active |
| US8560915B2 | 2D product code and method for detecting false decoding errors | Electricity | 1 | Active |
| US8477770B2 | Strict-sense minimal spanning switch non-blocking architecture | Electricity | 1 | Active |
| US9208117B2 | Method of accessing stored information in multi-framed data transmissions | Electricity | 0 | Active |
| US9264381B2 | Strict-sense minimal spanning switch non-blocking architecture | Electricity | 0 | Active |
| US8745113B2 | Pseudo-random bit sequence generator | Physics | 0 | Active |
| US9043685B2 | Method and apparatus for error-correction in and processing of GFP-T superblocks | Electricity | 0 | Active |
| US9063872B2 | Forward error correction with configurable latency | Electricity | 0 | Active |
| US8718215B2 | Method and apparatus for deskewing data transmissions | Electricity | 0 | Active |
| US9281911B1 | Method of multiple lane distribution (MLD) deskew | Electricity | 0 | Active |
| US8923441B2 | Context-sensitive overhead processor | Electricity | 0 | Active |
| US8645771B2 | Forward error correction with configurable latency | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.