Methods of on-chip memory partitioning and secure access violation checking in a system-on-chip
US8745724B2 · kind B2 · utility
3Cited by
3References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2011 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Dec 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods for partitioning memory into multiple secure and open regions are provided. The systems enable the security level of a given region to be determined without an increase in the time needed to determine the security level. Also, systems and methods for identifying secure access violations are disclosed. A secure trap module is provided for master devices in a system-on-chip. The secure trap module generates an interrupt when an access request for a transaction generates a security error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.