Methods for manufacturing semiconductor devices using etch stop dielectric layers and related devices
US8748251B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2012 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Nov 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
Abstract
A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.