Process for manufacturing an improved analog transistor

US8748270B1 · kind B1 · utility

Assignee

• SuVolta, Inc. · US

Inventors

• Lucian Shifren · San Jose, US
• Scott E. Thompson · Gainesville, US
• Paul E. Gregory · Palo Alto, US

Key dates

• Filing date: Jul 20, 2012
• Grant date: Jun 10, 2014
• Expiry date: Jul 20, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

An analog transistor useful for low noise applications or for electrical circuits benefiting from tight control of threshold voltages and electrical characteristics is described. The analog transistor includes a substantially undoped channel positioned under a gate dielectric between a source and a drain with the undoped channel not being subjected to contaminating threshold voltage implants or halo implants. The channel is supported on a screen layer doped to have an average dopant density at least five times as great as the average dopant density of the substantially undoped channel which, in turn, is supported by a doped well having an average dopant density at least twice the average dopant density of the substantially undoped channel.