Paul E. Gregory
26Patents
8h-index
29Co-inventors
75Inventor score
Filing activity: Jul 23, 1982 → Jul 17, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7022837B2 | Cellulose ethers and method of preparing the same | Chemistry; Metallurgy | 121 | Expired |
| US4952278A | High opacity paper containing expanded fiber and mineral pigment | Textiles; Paper | 111 | Expired |
| US4517714A | Nonwoven fabric barrier layer | Emerging Cross-Sectional Technologies | 109 | Expired |
| US4504977A | Disposable zoned surgical gown | Human Necessities | 57 | Expired |
| US6686464B1 | Cellulose ethers and method of preparing the same | Textiles; Paper | 43 | Expired |
| US4504978A | Disposable surgical gown sleeve | Human Necessities | 33 | Expired |
| US8421162B2 | Advanced transistors with punch through suppression | Electricity | 26 | Active |
| US8748270B1 | Process for manufacturing an improved analog transistor | Electricity | 20 | Active |
| US6970953B2 | System and method for terminating a bus | Emerging Cross-Sectional Technologies | 7 | Expired |
| US8614128B1 | CMOS structures and processes based on selective thinning | Electricity | 6 | Active |
| US9299698B2 | Semiconductor structure with multiple transistors having various threshold voltages | Electricity | 5 | Active |
| US9111785B2 | Semiconductor structure with improved channel stack and method for fabrication thereof | Electricity | 5 | Active |
| US8525271B2 | Semiconductor structure with improved channel stack and method for fabrication thereof | Electricity | 4 | Active |
| US9041126B2 | Deeply depleted MOS transistors having a screening layer and methods thereof | Electricity | 4 | Active |
| US9391076B1 | CMOS structures and processes based on selective thinning | Electricity | 1 | Active |
| US10718805B2 | Apparatus and methods for testing devices | Physics | 1 | Active |
| US6948007B2 | Method and apparatus for configuring integrated circuit devices | Electricity | 0 | Expired |
| US9508800B2 | Advanced transistors with punch through suppression | Electricity | 0 | Active |
| US5340405A | High solids liquid starch prepared by batch cooking | Chemistry; Metallurgy | 0 | Expired |
| US9263523B2 | Advanced transistors with punch through suppression | Electricity | 0 | Active |
| US10014387B2 | Semiconductor structure with multiple transistors having various threshold voltages | Electricity | 0 | Active |
| US9093469B2 | Analog transistor | Electricity | 0 | Active |
| US10325986B2 | Advanced transistors with punch through suppression | Electricity | 0 | Active |
| US9812550B2 | Semiconductor structure with multiple transistors having various threshold voltages | Electricity | 0 | Active |
| US10217838B2 | Semiconductor structure with multiple transistors having various threshold voltages | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.