Three-dimensional integrated circuit (3DIC)
US8749077B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2013 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Jul 23, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment 3DIC device includes a semiconductor chip, a die, and a polymer. The semiconductor chip includes a semiconductor substrate, wherein the semiconductor substrate comprises a first edge, and a low-k dielectric layer over the semiconductor substrate. The die is disposed over and bonded to the semiconductor chip. The polymer is molded onto the semiconductor chip and the die. The polymer includes a portion level with the low-k dielectric layer, wherein the portion of the polymer comprises a second edge vertically aligned to the first edge of the semiconductor substrate and a third edge contacting the low-k dielectric layer, wherein the second and the third edges are opposite edges of the portion of the polymer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.