SRAM multiplexing apparatus
US8750053B2 · kind B2 · utility
1Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2011 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Sep 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.