QoS management in the L2 cache
US8751746B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 2011 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Jun 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1605
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for assigning a QoS level to memory requests based on the number of currently outstanding memory requests. One or more processors of a processor complex issue memory requests to a L2 cache. The L2 cache controller assigns a QoS level to the memory request based on whether the number of outstanding memory requests is above or below a programmable threshold. If the number is above the threshold, then new requests typically do not impair processor performance since the processor is already waiting for a large number of previous memory requests, and so the new memory request is assigned a low priority level. If the number of outstanding memory requests is below the threshold, then the new memory request is assigned a high priority level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.