Memory address translation-based data encryption/compression
US8751830B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2012 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Mar 29, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit arrangement selectively stream data to an encryption or compression engine based upon encryption and/or compression-related page attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a memory access request for data in a memory page, such that attributes associated with the memory page in the data structure may be used to control whether data is encrypted/decrypted and/or compressed/decompressed in association with handling the memory access request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.