Hierarchical layout versus schematic (LVS) comparison with extraneous device elimination
US8751985B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2013 |
| Grant date | Jun 10, 2014 |
| Priority date | — |
| Expiry date | Mar 12, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Hierarchical layout versus schematic comparison with extraneous device elimination is provided. This includes obtaining a hierarchical layout netlist for a circuit design, the hierarchical layout netlist grouping arrayed devices of the circuit design into blocks repeated at a top level of a hierarchy of the hierarchical layout netlist. A modified hierarchical layout netlist defining active devices and connections thereof to top level pads of the circuit design is generated, in which extraneous devices are selectively removed from the obtained hierarchical layout netlist. The modified hierarchical layout netlist is verified against an input schematic netlist defining active devices of the circuit design and connections thereof to pads of the circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.