Dual-damascene process to fabricate thick wire structure
US8753950B2 · kind B2 · utility
3Cited by
16References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2012 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Mar 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.