Intra die variation monitor using through-silicon via
US8754412B2 · kind B2 · utility
1Cited by
13References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2012 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Jan 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising connecting IDVMON monitors with through silicon vias (TSV) to allow the monitors to be connected to probe pads located on the backside of the wafer. Because the backside of the wafer have significantly more space than the front side, the probe pads for IDVMON can be accommodated without sacrificing the silicon area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.