Three-dimensional semiconductor memory devices
US8754466B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2012 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Oct 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
Abstract
Three-dimensional (3D) semiconductor memory devices are provided. According to the 3D semiconductor memory device, a gate structure includes gate patterns and insulating patterns alternately stacked on a semiconductor substrate. A vertical active pattern penetrates the gate structure. A gate dielectric layer is disposed between a sidewall of the vertical active pattern and each of the gate patterns. A semiconductor pattern is disposed on the gate structure and is connected to the vertical active pattern. A string drain region is formed in a portion of the semiconductor pattern and is spaced apart from the vertical active pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.