Multi-chip wafer level package
US8754514B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2011 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Aug 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.