Flash memory
US8755231B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 2012 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Oct 19, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory is disclosed. The flash memory includes a flash memory chip; a serial-to-parallel converter for receiving and converting a serial data to a parallel data; and a data mode decision circuit connected to an output terminal of the serial-to-parallel converter for generating an inversion control signal through the parallel data and for applying an inversion processing to the parallel data and then outputting an inverted parallel data to the flash memory chip under the control of the inversion control signal. By converting the serial data to a parallel data and then writing the parallel data into the flash memory chip, a lower proportion of the inversion control signal to the total amount of data is achieved, and therefore less area is consumed while the same programming efficiency and average programming power is maintained compared with a flash memory adopting the bit inversion technique of the prior art.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.