Latch system applied to a plurality of banks of a memory circuit
US8755236B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2012 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Nov 4, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A latch system applied to a plurality of banks of a memory circuit includes a front latch circuit and a plurality of rear latch circuit. The front latch circuit is used for receiving a datum and a front latch enabling signal, and generating and outputting an intermediate signal according to the datum and the front latch enabling signal. Each rear latch circuit of the plurality of rear latch circuits is coupled to an output terminal of the front latch circuit for receiving the intermediate signal, and generating and outputting a rear latch datum to a corresponding bank of the plurality of banks according to the intermediate signal and a corresponding rear latch enabling signal, where only one rear latch enabling signal is enabled at any time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.