Read assist circuit for an SRAM
US8755239B2 · kind B2 · utility
15Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2011 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Jan 3, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.