Methods and apparatus for testing multiple-IC devices

US8756467B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Joseph S. Vaccaro · Chandler, US
• Michael E. Stanley · Mesa, US

Key dates

• Filing date: Nov 30, 2011
• Grant date: Jun 17, 2014
• Expiry date: Mar 11, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318513
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Embodiments of integrated circuits include a first input interconnect, a second input interconnect, an output interconnect, a shift register, a select register, a test access port (TAP) controller, and select register decode circuitry. The TAP controller is coupled to the first input interconnect and the select register, and the TAP controller is configured to shift a select value provided on the first input interconnect into the select register. The select register decode circuitry is configured to control, based on the select value, which of a plurality of test data output signals are provided to the output interconnect, where the plurality of test data output signals includes a first test data output signal and a second test data output signal. The first test data output signal is provided by the shift register, and the second test data output signal is received from a second integrated circuit on the second input interconnect.