Multiple-level memory cells and error detection
US8756481B2 · kind B2 · utility
4Cited by
4References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 1, 2013 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Feb 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory, modules and methods for using error detection with multi-level memory cells where the number of storage levels of the memory cells is an integer power of a non-binary prime number are provided. Additional circuit and methods are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.