Systems and methods for determining aging damage for semiconductor devices
US8756559B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2012 |
| Grant date | Jun 17, 2014 |
| Priority date | — |
| Expiry date | Oct 31, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes generating a circuit design and executing a simulation of the circuit design at a plurality of time slices. Type 1 damage and type 2 damage are determined for each time slice. A total type 1 damage is provided as a sum of the type 1 damage for all of the slices in which type 1 damage is greater than type 2 damage. A total type 2 damage is similarly added for the slices where the type 2 damage is dominant. A type 1 aging effect is determined based on the total type 1 damage. A type 2 aging effect is determined based on the total type 2 damage. The type 1 aging effect is added to the type 2 aging effect to obtain a total aging effect. The circuit design is tested using the total aging effect to determine if the circuit design provides adequate lifetime performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.