Manufacturing method of array substrate
US8759165B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2014 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Jan 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.