Method to form a CMOS image sensor
US8759225B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2012 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Sep 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.