Semiconductor memory device

US8759806B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Takeshi Yamaguchi · Sakai, JP
• Hirofumi Inoue · Kamakura, JP
• Reika Ichihara · Yokohama, JP
• Takayuki Tsukamoto · Yokohama, JP
• Takashi Shigeoka · Yokohama, JP
• Katsuyuki Sekine · Yokohama, JP
• Shinya Aoki · Kobe, JP

Key dates

• Filing date: Jul 13, 2011
• Grant date: Jun 24, 2014
• Expiry date: Jul 13, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/826

Abstract

A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line.