Transistor with threshold voltage set notch and method of fabrication thereof

US8759872B2 · kind B2 · utility

Assignee

• SuVolta, Inc. · US

Inventors

• Reza Arghavani · Scotts Valley, US
• Pushkar Ranade · Los Gatos, US
• Lucian Shifren · San Jose, US
• Scott E. Thompson · Gainesville, US
• Catherine de Villeneuve · San Jose, US

Key dates

• Filing date: Dec 17, 2010
• Grant date: Jun 24, 2014
• Expiry date: Dec 5, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/85

Abstract

A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low σVT) and VDD, so that the body bias can be tuned separately from VT for a given device.