Semiconductor arrangement with active drift zone
US8759939B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 31, 2012 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | May 8, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/112
Abstract
A semiconductor device arrangement includes a semiconductor layer and at least one series circuit with a first semiconductor device and a plurality of n second semiconductor devices, with n>1. The first semiconductor device has a load path and active device regions integrated in the semiconductor layer. Each second semiconductor device has active device regions integrated in the semiconductor layer and a load path between a first and second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each second semiconductor device has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. The arrangement further includes an edge termination structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.