Wafer level package structure and fabrication methods
US8759964B2 · kind B2 · utility
571Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2007 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Feb 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a package structure with reduced damage to semiconductor dies is provided. The method includes providing a die comprising bond pads on a top surface of the die; forming bumps on the bond pads of the die, wherein the bumps have top surfaces higher than the top surface of the die; mounting the die on a chip carrier, wherein the bumps are attached to the chip carrier; molding the die onto the chip carrier with a molding compound; de-mounting the chip carrier from the die; and forming redistribution traces over, and electrically connected to, the bumps of the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.