Inventor · Taichung, TW

Han-Ping Pu

136Patents
21h-index
109Co-inventors
93Inventor score

Filing activity: May 13, 1999 → Aug 2, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US8759964B2 Wafer level package structure and fabrication methods Electricity 571 Active
US6184573A Chip packaging Electricity 163 Expired
US6828665B2 Module device of stacked semiconductor packages and method for fabricating the same Electricity 163 Expired
US6593662B1 Stacked-die package structure Electricity 105 Expired
US6787918B1 Substrate structure of flip chip package Electricity 85 Expired
US7102239B2 Chip carrier for semiconductor chip Electricity 71 Expired
US7274088B2 Flip-chip semiconductor package with lead frame as chip carrier and fabrication method thereof Electricity 59 Expired
US7932601B2 Enhanced copper posts for wafer level chip scale packaging Electricity 56 Active
US6291264A Flip-chip package structure and method of fabricating the same Electricity 52 Expired
US6570249B1 Semiconductor package Electricity 48 Expired
US7772685B2 Stacked semiconductor structure and fabrication method thereof Electricity 41 Active
US6459144B1 Flip chip semiconductor package Electricity 39 Expired
US8288871B1 Reduced-stress bump-on-trace (BOT) structures Electricity 37 Active
US7247934B2 Multi-chip semiconductor package Electricity 29 Expired
US6281578A Multi-chip module package structure Electricity 28 Expired
US6400036B1 Flip-chip package structure and method of fabricating the same Electricity 28 Expired
US6891273B2 Semiconductor package and fabrication method thereof Electricity 26 Expired
US7208825B2 Stacked semiconductor packages Electricity 24 Expired
US6498054B1 Method of underfilling a flip-chip semiconductor device Electricity 24 Expired
US6849942B2 Semiconductor package with heat sink attached to substrate Electricity 23 Expired
US6610560B2 Chip-on-chip based multi-chip module with molded underfill and method of fabricating the same Electricity 22 Expired
US7023085B2 Semiconductor package structure with reduced parasite capacitance and method of fabricating the same Emerging Cross-Sectional Technologies 21 Expired
US6469897B2 Cavity-down tape ball grid array package assembly with grounded heat sink and method of fabricating the same Emerging Cross-Sectional Technologies 19 Expired
US6451625B1 Method of fabricating a flip-chip ball-grid-array package with molded underfill Electricity 18 Expired
US7638879B2 Semiconductor package and fabrication method thereof Electricity 17 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.