Semiconductor system and device for identifying stacked chips and method thereof
US8760181B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2010 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Jul 26, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor system for identifying stacked chips includes a first semiconductor chip and a plurality of second semiconductor chips. The first semiconductor chip generates a plurality of counter codes by using an internal clock or an external input clock and transmits slave address signals and the counter codes through a through-chip via. The second semiconductor chips are given corresponding identifications (IDs) by latching the counter codes for a predetermined delay time, compare the latched counter codes with the slave address signals, and communicate data with the first semiconductor chip through the through-chip via according to the comparison result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.