System for generating clock signal
US8760202B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2013 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | May 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for generating a clock signal includes a phase-locked loop (PLL) and a voltage storage circuit. The PLL includes a voltage-controlled oscillator (VCO) that generates a clock signal based on a control voltage. The voltage storage circuit includes a unity-gain amplifier (UGA) and first, second and third switches. The first switch connects an input terminal of the UGA and an input of the VCO to sample the control voltage before the PLL transitions from RUN mode to STOP mode. The second switch connects the input and output terminals of the UGA to store the sampled control voltage when the PLL is in STOP mode. The third switch connects the output terminal of the UGA to the input terminal of a low pass filter (LPF) to provide the stored control voltage to the LPF when the PLL transitions from the STOP mode to the RUN mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.