Graphics processing architecture employing a unified shader
US8760454B2 · kind B2 · utility
6Cited by
26References
11Claims
0Family size
Assignee
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Key dates
| Filing date | May 17, 2011 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | May 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data b a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.