Robust ESD protection circuit, method and design structure for tolerant and failsafe designs

US8760827B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• John B. Campi, Jr. · Colchester, US
• Shunhua T. Chang · South Burlington, US
• Kiran V. Chatty · Williston, US
• Robert J. Gauthier, Jr. · South Burlington, US
• Junjun Li · Williston, US
• Mujahid Muhammad · South Burlington, US

Key dates

• Filing date: Apr 15, 2009
• Grant date: Jun 24, 2014
• Expiry date: Jun 8, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002

Abstract

A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit includes a middle junction control circuit that turns off a top NFET of a stacked NFET electrostatic discharge (ESD) protection circuit during an ESD event.