Memory circuit
US8760926B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Jun 27, 2012 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Dec 12, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a memory circuit in which erroneous writing is less likely to occur at the time of power-on. A memory circuit (10) includes: a P-channel non-volatile memory element (15) for writing, to which a voltage is applied between a source and a drain thereof only during writing so as to write data; and an N-channel non-volatile memory element (16) for reading, which has a control gate and a floating gate provided in common to a control gate and a floating gate of the P-channel non-volatile memory element (15) and to which a voltage is applied to a source and a drain thereof only during reading so as to read the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.