Efficient static random-access memory layout
US8760927B2 · kind B2 · utility
8Cited by
1References
25Claims
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Key dates
| Filing date | Jul 25, 2012 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Mar 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with no well contacts within the memory array. Modern sub-micron CMOS structures have been observed to have reduced vulnerability to latchup. Chip area is reduced by providing no well contacts within the array. Wells of either or both conductivity types may electrically float during operation of the memory. In other implementations, extensions of the array wells into peripheral circuitry may be provided, with well contacts provided in those extended portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.