Semiconductor memory apparatus and data input/output method thereof
US8760960B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2012 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Aug 4, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory apparatus includes: a first bit line of to a first memory bank; a first middle input/output line configured to be electrically connected to the first bit line; a second bit line of a second memory bank; a second middle input/output line configured to be electrically connected to the second bit line; and a shared local input/output line configured to be electrically connected to the first and second middle input/output lines. A bank selection signal controls both the electrical connection between the shared local input/output line and the first middle input/output line and the electrical connection between the shared local input/output line and the second middle input/output line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.