Bounding box prefetcher
US8762649B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2011 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Oct 7, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data prefetcher in a microprocessor having a cache memory receives memory accesses each to an address within a memory block. The access addresses are non-monotonically increasing or decreasing as a function of time. As the accesses are received, the prefetcher maintains a largest address and a smallest address of the accesses and counts of changes to the largest and smallest addresses and maintains a history of recently accessed cache lines implicated by the access addresses within the memory block. The prefetcher also determines a predominant access direction based on the counts and determines a predominant access pattern based on the history. The prefetcher also prefetches into the cache memory, in the predominant access direction according to the predominant access pattern, cache lines of the memory block which the history indicates have not been recently accessed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.