Maintaining cache coherence in a multi-node, symmetric multiprocessing computer
US8762651B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2010 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Sep 9, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by the first compute node to other compute nodes a request for the cache line; if at least two of the compute nodes has a correct copy of the cache line, selecting which compute node is to transmit the correct copy of the cache line to the first node, and transmitting from the selected compute node to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.