Cross-layer system architecture design
US8762794B2 · kind B2 · utility
3Cited by
5References
5Claims
0Family size
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Key dates
| Filing date | Nov 18, 2011 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | May 11, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1482
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for cross-layer forgiveness exploitation include executing one or more applications using a processing platform that includes a first reliable processing core and at least one additional processing core having a lower reliability than the first processing core, modifying application execution according to one or more best-effort techniques to improve performance, and controlling parameters associated with the processing platform and the best-effort layer that control performance and error rate such that performance is maximized in a region of low hardware-software interference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.