Method, system, and computer program product for implementing multi-power domain digital / mixed signal verification and low power simulation
US8762906B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2010 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Jul 23, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.