Tiered schematic-driven layout synchronization in electronic design automation
US8762912B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2009 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Apr 22, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments provide a system that facilitates the creation of a layout from a schematic in an electronic design automation (EDA) application. During operation, the system performs a tiered comparison of the schematic and the layout. The tiered comparison includes a first tier that compares labels in the schematic and the layout. The tiered comparison also includes a second tier that compares first-level connectivity in the schematic and the layout. The tiered comparison further includes a third tier that determines a graph isomorphism between the schematic and the layout. After the tiered comparison is completed, the system provides a result of the tiered comparison to a user of the EDA application. Finally, the system enables repairs of mismatches in the result by the user through a graphical user interface (GUI) associated with the EDA application.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.