Methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness
US8762914B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2010 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | May 21, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness. Some embodiments identify or set parasitic constraint(s) and compare the electrical parasitic(s) with corresponding parasitic constraint(s) to determine whether the parasitic constraints are met. Some embodiments first identify, determine, or update the physical data of a component of a partial layout and characterize the electrical parasitics associated with the physical data of the component. Some embodiments identify or determine some schematic level performance constraints and estimate parasitic constraints based on schematic simulation results and the performance constraints; the estimated parasitic constraints are then compared with the corresponding electrical parasitics to determine whether the constraints are satisfied. Some embodiments further map schematic level parasitic constraints to a physical design representation and then compares the mapped parasitic constraints with corresponding electrical constraints to determine whether the mapped constraints are met.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.