System for reducing leakage power of electronic circuit
US8762922B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2013 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Oct 13, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for reducing leakage power of an electronic circuit design, where the circuit design includes multiple timing paths, each timing path made up of multiple cells, using an electronic design automation (EDA) tool. The EDA tool includes a processor that chooses a first replacement cell for replacing a first cell in a first timing path when timing slack is not available in the first path, where a width and threshold voltage of the first replacement cell are greater than a width and threshold voltage of the first cell. The processor then replaces the first cell with the first replacement cell when the overall power consumption of the first replacement cell is less than that of the first cell, and when the timing slack is available for replacing the first cell with the first replacement cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.