Shallow trench isolation recess repair using spacer formation process
US8765491B2 · kind B2 · utility
6Cited by
11References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2010 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Jul 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device includes forming a spacer layer over a plurality of transistor gate structures, the transistor gate structures being formed over both active and shallow trench isolation (STI) regions of a substrate. The spacer layer is subjected to a directional etch so as to form sidewall spacers adjacent the plurality of transistor gate structures, and a horizontal fill portion of the spacer layer remains in one more recesses present in the STI regions so as to substantially planarize the STI region prior to subsequent material deposition thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.