Stress engineered multi-layers for integration of CMOS and Si nanophotonics

US8765536B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Solomon Assefa · Ossining, US
• Tymon Barwicz · Yorktown Heights, US
• Swetha Kamlapurkar · Yorktown Heights, US
• Marwan H. Khater · New York, US
• Steven M. Shank · Jericho, US
• Yurii A. Vlasov · Katonah, US

Key dates

• Filing date: Sep 28, 2012
• Grant date: Jul 1, 2014
• Expiry date: Sep 28, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10F39/103

Abstract

A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device.