Non-volatile memory device having vertical structure and method of manufacturing the same
US8765551B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2012 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Dec 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
Abstract
According to an example embodiment, a non-volatile memory device includes a semiconductor layer pattern on a substrate, a plurality of gate patterns and a plurality of interlayer insulating layer patterns that are alternately stacked along a side wall of the semiconductor layer pattern, and a storage structure between the plurality of gate patterns and the semiconductor layer pattern. The semiconductor layer pattern extends in a vertical direction from the substrate. The gate patterns are recessed in a direction from a side wall of the interlayer insulating layer patterns opposing the side wall of the semiconductor layer pattern. A recessed surface of the gate patterns may be formed to be vertical to a surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.