Active tiling placement for improved latch-up immunity

US8765607B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Robert S. Ruth · Austin, US
• Mark A. Kearney · Austin, US
• Bernard J. Pappert · Austin, US
• Juxiang Ren · Austin, US
• Jeff L. Warner · Austin, US

Key dates

• Filing date: Jun 1, 2011
• Grant date: Jul 1, 2014
• Expiry date: Jun 16, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device includes CMP dummy tiles (36) that are converted to active tiles by forming well regions (42) at a top surface of the dummy tiles, forming silicide (52) on top of the well regions, and forming a metal interconnect structure (72, 82) in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.